1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a nonvolatile ferroelectric memory device and a method of fabricating a nonvolatile ferroelectric memory device.
2. Discussion of the Related Art
In general, a nonvolatile ferroelectric memory, i.e., a ferroelectric random access memory (FRAM), has a data processing speed equal to a dynamic random access memory (DRAM) and retains data when power is turned OFF. The FRAM and DRAM memories have similar structures, but the FRAM includes a ferroelectric capacitor having a high residual polarization characteristic. The residual polarization characteristic permits retention of data when an applied electric field is removed.
FIG. 1 is a diagram showing a hysteresis loop of a ferroelectric material according to the related art. In FIG. 1, an amount of polarization within a ferroelectric material is induced when an electric field is applied to the ferroelectric material. However, an amount of residual (remnant) polarization remains when the electric field is removed from the ferroelectric material. Accordingly, an amount of electric charge may be maintained within the ferroelectric material, i.e., at “a” and “d” states, when the electric field is removed. Thus, data may be stored in the ferroelectric material without being erased due to the residual polarization (or spontaneous polarization) of the ferroelectric material. A nonvolatile ferroelectric memory cell is used as a memory device by correlating the “d” and “a” states to a logical “1” and “0,” respectively.
FIG. 2 is a schematic diagram of a unit cell of a nonvolatile ferroelectric memory device according to the related art. In FIG. 2, a nonvolatile ferroelectric memory device includes a bitline B/L formed along a first direction, a wordline W/L formed along a second direction perpendicular to the first direction to cross the bitline B/L, a plate line P/L spaced apart from the wordline W/L along the second direction, a transistor T1 having a gate connected to the wordline W/L and a source connected to the bitline B/L, and a ferroelectric capacitor FC1. A first terminal of the ferroelectric capacitor FC1 is connected to a drain of the transistor T1 and a second terminal of the ferroelectric capacitor FC1 is connected to the plate line P/L.
FIG. 3A is a timing diagram showing a write mode operation of a nonvolatile ferroelectric memory device according to the related art, and FIG. 3B is a timing diagram showing a read mode operation of a nonvolatile ferroelectric memory device according to the related art.
In FIG. 3A, during the write mode, an externally applied chip enable signal CSBpad is enabled from a HIGH state to a LOW state. At the same time, if a write enable signal WEBpad is applied from a HIGH state to a LOW state, the write mode starts. Subsequently, if address decoding in the write mode starts, a pulse applied to a corresponding wordline is transited from a LOW state to a HIGH state to select a cell.
A HIGH signal in a certain period and a LOW signal in a certain period are sequentially applied to a corresponding plate line P/L in a period where the wordline W/L is maintained at HIGH state. To write a logic value “1” or “0” in the selected cell, a HIGH signal or a LOW signal synchronized with the write enable signal WEBpad is applied to a corresponding bitline B/L. Accordingly, a HIGH signal is applied to the bitline B/L, and if the LOW signal is applied to the plate line P/L in a period where the signal applied to the wordline W/L is HIGH, a logic value “1” is written to the ferroelectric capacitor. A LOW signal is applied to the bitline B/L, and if the signal applied to the plate line P/L is HIGH, a logic value “0” is written to the ferroelectric capacitor.
In FIG. 3B, if an externally applied chip enable signal CSBpad is enabled from a HIGH state to a LOW state, all bitlines B/L become equipotential to a low voltage by an equalizer signal EQ before a corresponding wordline W/L is selected. Then, the respective bitline B/L becomes disabled and an address is decoded, and the LOW signal is transited to the HIGH signal in the corresponding wordline W/L according to the decoded address so that a corresponding cell is selected. The HIGH signal is applied to the plate line P/L of the selected cell to remove data corresponding to the logic value “1” stored in the ferroelectric memory. If the logic value “0” is stored in the ferroelectric memory, corresponding data is not removed.
The removed data and the data that is not removed are output as different values by the ferroelectric hysteresis loop, so that a sensing amplifier senses the logic value “1” or “0”. Accordingly, if the data is removed, the “d” state is transited to an “f” state as shown in the hysteresis loop of FIG. 1, and if the data is not removed, the “a” state is transited to the “f” state. Thus, if the sensing amplifier is enabled after a set time has elapsed, the logic value “1” is output in case that the data is removed while the logic value “0” is output in case that the data is not removed. After the sensing amplifier outputs data, to recover the data to the original data, the plate line P/L becomes disabled from a HIGH state to a LOW state where the HIGH signal is applied to the corresponding wordline W/L.
However, the nonvolatile ferroelectric memory device according to the related art is problematic. For example, when the semiconductor chip is highly integrated, a distance between intervals of adjacent bit lines decreases and cross-talk capacitance between the adjacent bit lines increases, thereby decreasing a sensing margin. Accordingly, there are limits for increasing the intervals between adjacent bit lines and increasing the sensing margin.